Executive Summary
Bernhard Quendt, CTO of Thales Group, delivered a compelling presentation at RISC-V Summit Europe 2025 on May 28th, 2025 on the strategic adoption of open-source hardware (OSH), particularly RISC-V and the CVA6 core, to build sovereign and reliable supply chains in safety- and mission-critical domains. The talk emphasized how tightening geopolitical controls—export restrictions from both U.S.-aligned and China-aligned blocs—are accelerating the need to decouple from proprietary IP.
Quendt highlighted three technical thrusts in this initiative: an open-source-based spaceborne computing platform based on CVA6, a compact industrial-grade CVA6-based microcontroller (CVA62) for embedded systems, and a forthcoming CVI64 core with MMU support for secure general-purpose OSes.
Thales is not adopting OSH merely as a cost-cutting measure. Rather, it views open hardware as foundational—alongside AI acceleration, quantum computing, and secure communications—for enabling digital sovereignty, reducing integration costs, and maintaining complete control over high-assurance system architectures.
Three Critical Takeaways
1. CVA6-Based Spaceborne Computing Platform
Technical Overview
Thales Alenia Space has developed a modular onboard computer based on the CVA6 64-bit RISC-V core. This system incorporates secure open-source root-of-trust blocks and vector accelerators. The platform supports mixed-criticality software and is tailored for the unique reliability and certification needs of space environments.
The modularity of the platform allows faster design iteration and decoupling of hardware/software verification cycles—critical benefits in aerospace development.
Assessment
The strategy is forward-leaning but not without risk. Toolchains and verification flows for open-source processors remain less mature than those in the Arm or PowerPC ecosystem. Furthermore, CVA6 is not yet hardened against radiation effects (e.g., single event upsets or total ionizing dose), which poses challenges for LEO and deep-space applications.
Thales likely mitigates this through board-level fault tolerance and selective redundancy, though such architectural decisions were not disclosed.
Market Context
This approach diverges from legacy reliance on processors like LEON3 (SPARCv8) or PowerPC e500/e6500, which are radiation-tolerant and supported by ESA/NASA toolchains. The open RISC-V path offers increased configurability and transparency at the expense of hardened IP availability and TRL maturity.
Quantitative Support
While specific metrics were not shared, RISC-V-based radiation-tolerant designs typically aim for performance in the 100–500 DMIPS range. Proprietary IP licenses for space-qualified cores can exceed $1–2 million per program, underscoring the potential cost advantage of open-source silicon.
2. CVA62: Low-Area, Safety-Ready Microcontroller
Technical Overview
Thales introduced CVA62, a 32-bit microcontroller derivative of CVA6, targeting embedded systems and industrial IoT. CVA62 is designed on TSMC 5nm and adheres to ISO 26262 safety principles, aiming for ASIL-B/D applicability. Its RTL is formally verified and publicly auditable.
It supports the RV32IMAC instruction set, features a configurable pipeline depth, and prioritizes area and power efficiency. Its release aligns with growing demand for safety-certifiable open cores.
Assessment
A formally verified open-source MCU with ISO 26262 alignment is a strong differentiator—especially for defense, automotive, and infrastructure markets. However, achieving full ASIL-D certification also depends on qualified toolchains, documented failure modes, and compliance artifacts. The current RISC-V ecosystem has yet to meet these rigorously.
Still, the availability of a verified baseline—combined with collaboration-friendly licensing—could enable safety qualification through industry-specific efforts.
Competitive Context
CVA62 competes with Cortex-M7 and SiFive E31/E51 in the deterministic MCU space. While Arm cores offer rich toolchains and pre-certified software stacks, CVA62 provides transparency and configurability, with the tradeoff of less polished ecosystem support.
| Feature | CVA62 | Cortex-M7 |
|---|---|---|
| ISA | RISC-V (RV32IMAC) | Armv7E-M |
| Pipeline | Configurable | Fixed 6-stage |
| MMU Support | No | No |
| Open Source | Yes | No |
| ISO 26262 Alignment | Planned | Available (via toolchain vendors) |
| Target Process | TSMC 5nm | 40nm–65nm typical |
Quantitative Support
Public benchmarks for RV32-class cores show CVA62 class devices achieving 1.5–2.0 CoreMark/MHz depending on configuration. Power efficiency data is pending silicon tape-out but is expected to improve over larger legacy MCUs due to 5nm geometry.
3. CVI64: MMU-Enabled RISC-V Application Core
Technical Overview
Thales is collaborating on CVI64, a 64-bit RISC-V core with memory management unit (MMU) support and a clean-slate deterministic design philosophy. The first silicon is targeted for Technology Readiness Level 5 (component validation in relevant environment) by Q3 2025.
CVI64 is intended to support real-time Linux and deterministic hypervisors, with applications in avionics, defense systems, and certified industrial platforms.
Assessment
Adding MMU support unlocks Linux-class workloads—but increases architectural complexity. Issues like page table walk determinism, cache coherence, and privilege transitions must be tightly constrained in safety contexts. Out-of-order execution, if implemented, would further complicate timing analysis.
Early ecosystem maturity will likely lag that of SiFive U-series or Arm Cortex-A cores, but CVI64 may find niche adoption where auditability and customization trump software availability.
Competitive Context
CVI64 enters a field occupied by SiFive S7/S9, Andes AX45, and Arm Cortex-A53/A55. Unlike these, CVI64 will be fully open and verifiable. This suits users requiring full-stack trust anchors—from silicon up to operating system.
| Feature | CVI64 | SiFive S7 | Cortex-A53 |
|---|---|---|---|
| ISA | RV64GC | RV64GC | Armv8-A |
| MMU | Yes | Yes | Yes |
| Execution Model | In-order (planned) | In-order | Out-of-order |
| Target Frequency | TBD (~1 GHz class) | 1.5–2.0 GHz | 1.2–1.5 GHz |
| Open Source | Yes (100%) | Partial | No |
Quantitative Support
SiFive U84-based SoCs have reached 1.5 GHz on 7nm. CVI64 will likely debut at lower performance (~800–1000 MHz) due to early-phase optimizations and tighter deterministic design goals.
Final Thoughts
Thales’s adoption of open-source silicon reflects a strategic shift across defense and aerospace sectors. OSH enables sovereignty, customization, and long-term maintenance independence—critical in an era of increasingly politicized semiconductors.
Yet major challenges persist: toolchain immaturity, limited availability of safety-certifiable flows, and uncertain community governance. Organizations pursuing this path should adopt a phased integration model—deploying OSH first in non-critical components while building verification and integration expertise in parallel.
Significant investment will be required in:
- Formal verification frameworks (e.g., SymbiYosys, Boolector, Tortuga Agilis)
- Mixed-language simulation environments (e.g., Verilator, Cocotb)
- Cross-industry ecosystem building and long-term funding models
Thales is making a long-term bet on auditability and openness in silicon. If the RISC-V ecosystem can deliver the tooling and robustness demanded by regulated industries, it could catalyze a new wave of mission-grade open architectures. The opportunity is real—but so is the engineering burden.