Executive Summary
In his presentation at Direct Connect 2025 on April 29th, 2025, Navid Shahriari, Executive Vice President and General Manager of Intel Foundry’s integrated technology development and factory network, outlined a comprehensive roadmap for advanced packaging technologies under the umbrella of heterogeneous integration. The talk emphasized Intel Foundry’s evolution into an OSAT (Outsourced Semiconductor Assembly and Test) partner of choice, offering full-stack flexibility—from design to manufacturing—while addressing critical challenges in quality, yield, and cost.
Shahriari positioned heterogeneous integration as a transformative force powering the AI revolution, moving from a niche concept to a mainstream necessity. His technical roadmap included enhancements to EMIB (Embedded Multi-die Interconnect Bridge), the introduction of Foros R/B, hybrid bonding (Forvorous Direct), and innovations in power delivery, thermal management, and co-packaged optics. The strategic goal is clear: provide scalable, flexible, and cost-effective packaging solutions that meet the extreme demands of next-generation AI systems.
Three Critical Takeaways
1. Enhanced EMIB with TSV-Based Power Delivery (EMIT)
Technical Explanation
Intel introduced EMIT, an enhancement to its existing EMIB (Embedded Multi-die Interconnect Bridge) technology. EMIB enables high-density interconnect between multiple die using a silicon bridge embedded in the organic substrate. EMIT adds Through-Silicon Vias (TSVs) to this architecture, enabling direct power delivery through the substrate rather than relying on thin metal layers in the bridge itself.
This addresses IR drop issues that become significant at higher data rates (e.g., HBM4 operating at 12 Gbps per pin). By routing power vertically through TSVs, EMIT reduces both AC and DC noise, improving signal integrity and performance stability.
Key specs:
- Supports HBM4 and UCIe (Universal Chiplet Interconnect Express)
- Scalable pitch down to 9µm
- Panel-based DLAST process enables large-scale integration (up to 80x80mm² packages)
Critical Assessment
The addition of TSV-based power delivery represents a pragmatic solution to a well-known limitation of 2.5D interposer architectures. While silicon interposers offer excellent interconnect density, their use for power distribution has always been suboptimal due to limited metal thickness and current-carrying capacity.
By embedding vertical TSVs directly into the EMIB structure, Intel effectively combines the best of both worlds: the cost and scalability benefits of panel-based packaging with the robustness of TSV-based power rails. However, the long-term reliability of these TSVs under high current densities remains a concern, especially for kilowatt-level AI chips.
Competitive/Strategic Context
Compared to TSMC’s CoWoS-S, which uses a full silicon interposer with redistribution layers, EMIB/EMIT offers better cost scaling because it avoids wafer-level reticle stitching constraints. TSMC’s approach excels in maximum bandwidth but suffers from lower throughput and higher costs at scale.
| Feature | Intel EMIB/EMIT | TSMC CoWoS-S |
|---|---|---|
| Interconnect Type | Embedded Silicon Bridge | Full Silicon Interposer |
| Power Delivery | TSV-enhanced | Thin Metal Layers |
| Cost Scaling | Good | Poor |
| Max Reticle Size | Panel-scale | Wafer-scale |
Quantitative Support
- Over 16 million units of EMIB already shipped
- Targeting 8x reticle size by 2026 and beyond
- Supports up to 12 HBM stacks
2. Hybrid Bonding (Forvorous Direct): 9µm Pitch Copper-to-Copper Bonding
Technical Explanation
Intel announced progress in hybrid bonding, specifically Forvorous Direct, achieving a 9µm pitch copper-to-copper bonding for 3D stacking. This allows direct metallurgical bonding between dies without microbumps, reducing parasitics and enabling ultra-high-density interconnects.
Hybrid bonding is crucial for future chiplet architectures, where logic-on-logic or logic-on-memory stacking is needed with minimal latency and power overhead.
Critical Assessment
Hybrid bonding is widely regarded as the next frontier in advanced packaging. Intel’s reported yield improvements are promising, but real-world reliability metrics remain sparse. Reliability testing typically requires multiple data turns across temperature, voltage, and mechanical stress cycles—data that was not shared.
Another consideration is alignment accuracy: achieving consistent bond quality across millions of pads at 9µm pitch is non-trivial and will require precision equipment and control algorithms. Intel’s roadmap suggests production readiness within a year, which aligns with industry expectations.
Competitive/Strategic Context
Intel competes here with TSMC’s BONDOS and Samsung’s Hybrid Bonding offerings. Both foundries have demonstrated similar pitches (down to ~6–7µm), though commercial deployment is still limited.
| Feature | Intel Forvorous Direct | TSMC BONDOS |
| Bond Type | Cu-Cu | Cu-Cu |
| Pitch | 9µm | 6–7µm |
| Production Readiness | Sampling now, 2026 target | Limited availability |
| Yield Data | Improving | Not publicly available |
Quantitative Support
- Achieved 9µm pitch hybrid bonding
- High-volume sampling underway
- Targeting production readiness in 2026
3. Known-Good Die (KGD) Testing & Singulated Die Services
Technical Explanation
As chiplets and multi-die packages become more complex, ensuring known-good die (KGD) becomes mission-critical. Intel highlighted its mature singulated die test capability, developed over a decade, supporting advanced probing and burn-in processes.
This includes custom test flows, integration with ATE ecosystems (like Teradyne or Advantest), and support for customer-specific test vectors and protocols.
Critical Assessment
The economic impact of defective dies in multi-die systems can be catastrophic. Intel’s singulated die test infrastructure is a major differentiator, especially when compared to OSATs that lack such capabilities or rely on less rigorous binning strategies.
However, the cost and time overhead of exhaustive KGD testing must be balanced against yield improvements. For example, if a system integrates 100+ die, even a 1% defect rate leads to a 36% overall yield loss—highlighting the importance of near-perfect KGD assurance.
Competitive/Strategic Context
Most third-party OSATs do not offer end-to-end KGD services, instead focusing on assembly rather than pre-packaging test. Intel positions itself uniquely by offering KGD as a service, either standalone or as part of a broader flow.
| Capability | Intel KGD Service | Typical OSAT Offering |
| Pre-Packaging Test | Yes | No |
| Burn-In Capabilities | Yes | Rare |
| Custom Test Flow | Supported | Limited |
| Integration with ATE | Deep | Basic |
Quantitative Support
- Over 10 years of production experience
- Piloting with select customers showing strong results
- Essential for managing cost in multi-chiplet, high-reticle designs
Conclusion
Navid Shahriari’s presentation painted a compelling picture of Intel Foundry’s ambitions to lead in the post-Moore’s Law era through advanced packaging and heterogeneous integration. From enhanced EMIB with TSV power delivery to hybrid bonding and KGD-centric test strategies, the roadmap reflects a deep understanding of the evolving needs of AI-driven compute architectures.
While the technical claims are backed by impressive deployment figures (e.g., 16M+ EMIB units shipped), the true validation will come from sustained yield improvements, reliability data, and ecosystem adoption. Intel Foundry’s ability to offer modular, OSAT-like flexibility while maintaining world-class packaging innovation puts it in a unique position to serve both traditional and emerging semiconductor markets.
As AI continues to push the boundaries of system complexity and power density, Intel Foundry’s back-end roadmap may well define the next generation of compute platforms—not just for Intel, but for the broader ecosystem seeking alternatives to monolithic scaling.