Executive Summary
At the Direct Connect 2025 keynote on April 29th, 2025, Intel CEO Lip-Bu Tan outlined a bold and necessary pivot: transforming Intel into a leading global foundry. His central message was clear—innovation depends on deep collaboration, customer-centricity, and sustained execution.
Intel is now building its future on four interlocking pillars:
- Process Technology Leadership
- Advanced Packaging at Scale
- Open Ecosystem Enablement
- Manufacturing Scalability and Trust
Tan emphasized Intel’s singular position as the only U.S.-based company with both advanced R&D and high-volume manufacturing capabilities in logic and packaging. Key partnerships with Synopsys, Cadence, Siemens EDA, and PDF Solutions aim to establish a truly open and modern foundry model—one that is competitive with TSMC and Samsung on technology, but differentiated by geography, trust, and strategic alignment with national priorities.
This strategic direction was substantiated by in-depth presentations from executives Naga Shakerin and Kevin O’Rourke, detailing progress on Intel 18A, advanced packaging (EMIB and Foveros), and the ecosystem infrastructure supporting customer design and yield enablement.
Three Critical Takeaways
1. Intel 18A: Gate-All-Around and Backside Power, Delivered at Scale
Technology Leadership
Intel 18A introduces gate-all-around (GAA) RibbonFET transistors and PowerVia, a backside power delivery network that routes power beneath the transistor layer, freeing up top-side metal layers for signal routing.
Key benefits:
- ~10% improvement in cell utilization
- ~4% performance uplift at iso-power
- ~30% density gain over Intel 20A
This architecture is tailored for compute-intensive, bandwidth-constrained domains like AI training, HPC, and edge inference, where energy efficiency and signal integrity dominate system-level constraints.
Competitive Perspective
While Samsung (3GAE) and TSMC (N2) also offer GAA, Intel is first to pair GAA with backside power in a commercially viable, high-volume node. This combination offers a compelling differentiator in power efficiency and routing simplicity, particularly for multi-die systems and 3D packaging strategies.
| Feature | Intel 18A | TSMC N2 | Samsung 3GAE |
|---|---|---|---|
| GAA | Yes | Yes | Yes |
| Backside Power | Yes | No | No |
| High EUV Use | Yes | Yes | Moderate |
| U.S. Foundry Option | Yes | No | No |
Execution Status
- Risk production in progress; volume production planned for 2025
- Yield indicators tracking toward target defect densities
- 100+ customer engagements under NDA
- Early silicon achieving ~90–95% of performance targets
2. Advanced Packaging as the New Integration Frontier
Platform Capability
Intel is doubling down on heterogeneous integration via:
- EMIB (Embedded Multi-die Interconnect Bridge): 2.5D packaging enabling high-bandwidth, low-latency links between chiplets
- Foveros: 3D stacking with active interposers, TSVs, and logic-on-logic die integration
New variants include:
- EMIB-T: Incorporating TSVs for enhanced vertical power delivery
- Foveros R/B/S: Feature-integrated versions supporting voltage regulation and embedded passive elements (e.g., MIMCAPs)
Intel now supports reticle-scale and sub-reticle tile stitching, with packages up to 120×188 mm², enabling compute fabrics, stacked DRAM, and integrated accelerators in single systems-in-package.
Strategic Implication
Advanced packaging is Intel’s bridge between Moore’s Law economics and modular, chiplet-based innovation. While CoWoS and X-Cube offer similar capabilities, Intel’s advantage lies in its U.S.-based, vertically integrated packaging supply chain—a critical factor for defense, aerospace, and regulated markets.
| Metric | Intel EMIB/Foveros | TSMC CoWoS | Samsung X-Cube |
|---|---|---|---|
| Reticle Stitching | Yes | Partial | No |
| TSV-Enabled | Yes | Limited | Yes |
| Power Integrity Enhancements | Yes | Yes | Moderate |
| Domestic Packaging | Yes | No | No |
Execution Status
- Microbump pitch below 25 μm in production
- Inline ML-based defect detection reduces test and soak costs by >20%
- Packaging roadmap aligned with 18A and 14A node cadence
3. Ecosystem Enablement: Toward a Modern, Open Foundry
Infrastructure Build-Out
Intel is transitioning from an internal IDM model to an open, customer-facing foundry supported by industry-standard tools and workflows. Key developments:
- PDK Access: 18A and 14A enabled through Synopsys and Cadence
- Design Signoff: Siemens Calibre certified on 18A
- Yield Analytics: PDF Solutions integrated into ramp flow, reducing yield learning cycles
Intel Foundry aims to meet external customer expectations on design readiness, IP portability, and predictable tapeout schedules—areas where TSMC has set the bar.
Market Context
While Intel’s ecosystem is still maturing, its combination of geopolitical alignment, manufacturing transparency, and customer co-design programs creates a differentiated value proposition—especially for companies operating in defense, automotive, or AI infrastructure sectors that require U.S.-based capacity.
| Capability | Intel Foundry | TSMC | Samsung |
|---|---|---|---|
| External IP Support | Moderate | Extensive | High |
| Open PDK Access | Yes | Yes | Yes |
| AI Yield Tuning | Yes (PDF) | Yes | Emerging |
| Domestic Compliance | Full | None | Partial |
Execution Status
- 18A tapeouts supported via pre-qualified tool flows
- Over 100 design teams actively engaged across customer and internal tapeouts
- Full stack support (RTL to GDSII to HVM) expected by Q4 2025
Conclusion
Intel’s 2025 foundry strategy marks a decisive inflection point for the company—and for the U.S. semiconductor industry at large. With 18A, Foveros, and an open design ecosystem now moving into execution, Intel is not merely catching up, but defining a new kind of foundry model: one built on technical excellence, geographic trust, and systems-level collaboration.
However, the path forward will demand discipline in yield ramping, transparency in roadmap delivery, and deep ecosystem support. For engineering leaders and CTOs, Intel presents a strategic alternative—not only in performance, but in resilience and sovereignty.
In a world where manufacturing location, IP control, and system integration are as important as process node performance, Intel Foundry may well become the preferred partner for the next generation of compute platforms.