Executive Summary
In this presentation at Direct Connect 2025 on April 29th, 2025, Intel’s Vice President and GM Ben Sell, along with Myung-Hee Na, outlined the company’s roadmap for next-generation process technologies. The central thesis revolves around extending Moore’s Law through architectural innovation—particularly via gate-all-around (GAA) transistors (RibbonFET) and backside power delivery (PowerVia). These innovations aim to deliver significant performance-per-watt improvements while enabling advanced 3D integration for AI and high-performance computing workloads.
The roadmap includes:
- Intel 18A: First production GAA node with PowerVia, targeting Q4 2025 volume production.
- Intel 18AP: Enhanced version of 18A with better transistor performance and VT types, slated for late 2026.
- Intel 18APT: Base die for 3D ICs with TSVs optimized for signal and power, entering risk production in 2026.
- Intel 14A: Full-node scaling over 18A with second-gen RibbonFET and PowerVia, expected in 2027.
The talk also emphasized technology co-optimization, system-aware design, and long-term R&D into post-silicon materials like molybdenum disulfide (MoS₂) and alternative packaging techniques.
Three Critical Takeaways
1. RibbonFET + PowerVia: A Dual Innovation for Performance and Density
Technical Explanation
Intel’s RibbonFET is a gate-all-around (GAA) transistor architecture that improves electrostatic control, particularly beneficial for low-voltage operation. Each transistor comprises four stacked ribbons, allowing for better current modulation and reduced leakage.
PowerVia rethinks traditional front-side power routing by moving it to the backside of the wafer. This approach:
- Reduces voltage drop from bump to transistor
- Relaxes lower-layer metal pitch requirements (from <25nm to ~32nm)
- Improves library cell utilization
This dual innovation delivers:
- >15% performance improvement at same power
- 1.3x chip density improvement over Intel 3
Critical Assessment
The combination of RibbonFET and PowerVia addresses two major bottlenecks: transistor scalability and power delivery efficiency. However, the cost implications of adding backside metallization are non-trivial. Intel claims they offset this via simplified front-end patterning using EUV lithography.
One unstated assumption is the long-term yield stability of these complex processes, especially as they scale into multi-die stacks and 3D ICs. Early data shows yields matching or exceeding historical Intel nodes, but sustained HVM (high-volume manufacturing) yields remain to be seen.
Competitive/Strategic Context
Competitors like TSMC and Samsung are also pursuing GAA (MBCFET), with TSMC opting for nanosheet FETs. Samsung has announced Gate-All-Around for their 3nm node. However, Intel’s early integration of backside power delivery is unique and could offer advantages in chiplet-based designs and AI accelerators where power delivery and thermal management are critical.
Quantitative Support
| Metric | Intel 18A vs. Intel 3 |
|---|---|
| Performance gain (same power) | >15% |
| Chip density improvement | 1.3x |
| Lower metal pitch relaxation | <25nm → 32nm |
| SRAM area reduction (high-density) | ~89% |
2. System-Aware Co-Optimization for AI Workloads
Technical Explanation
Myung-Hee Na highlighted the shift from Design-Technology Co-Optimization (DTCO) to System-Technology Co-Optimization (STCO). This approach involves:
- Understanding workload-specific compute needs (especially AI)
- Co-designing silicon, packaging, and system architecture together
- Enabling 3D ICs with fine-pitch TSVs and hybrid bonding
Intel’s Intel 18APT is designed specifically as a base die for 3D integration, offering:
- 20–25% compute density increase
- 25–35% power reduction
- ~9x increase in die-to-bandwidth density
Critical Assessment
This marks a strategic pivot toward domain-specific optimization, aligning with trends in AI hardware acceleration and heterogeneous computing. However, implementing STCO requires deep collaboration across the stack—from EDA tools to OS-level scheduling—and may introduce new layers of complexity in verification and toolchain support.
While promising, Intel’s roadmap lacks concrete details on software enablement and toolchain readiness—key factors in realizing the benefits of co-optimized systems.
Competitive/Strategic Context
Other players like AMD and NVIDIA have pursued similar strategies via chiplet architectures and NVLink interconnects, respectively. However, Intel’s focus on bottom-up co-integration (silicon + packaging + system) sets them apart. The challenge will be maintaining coherence between rapidly evolving AI algorithms and fixed silicon pipelines.
Quantitative Support
| Feature | Intel 18APT Improvement |
| Compute density | +20–25% |
| Power consumption | -25–35% |
| Die-to-bandwidth density | ×9 increase |
3. High-NA EUV: Cost Reduction Through Simplified Patterning
Technical Explanation
Intel is leveraging high-NA EUV to reduce process complexity and cost. For example, certain patterns previously requiring three EUV exposures and ~40 steps can now be achieved with a single pass using high-NA EUV.
This not only shortens the process flow but also allows for metal layer depopulation, which can improve RC delay and overall performance.
Critical Assessment
The move to high-NA EUV is both technically sound and strategically necessary given the rising cost of multi-patterning. However, high-NA tools are still rare and expensive. ASML currently produces them in limited quantities, and full deployment across Intel’s foundry network will take time.
Additionally, there’s an implicit assumption that design rules can accommodate relaxed geometries without sacrificing performance—this remains to be validated in real-world SoC implementations.
Competitive/Strategic Context
TSMC and Samsung are also investing heavily in high-NA EUV, but Intel appears to be ahead in its integration timeline, particularly for logic applications. Their use case—combining high-NA with PowerVia—is novel and could provide a cost-performance edge in high-margin segments like client and server CPUs.
Quantitative Support
| Approach | Steps Required | Metal Layers Used |
| Traditional Multi-Pass EUV | ~40 | Multiple |
| High-NA EUV Single Pass | ~10–15 | Reduced (depopulated) |
Conclusion
Intel’s Direct Connect 2025 presentation paints a compelling picture of process innovation driven by architectural foresight. With RibbonFET, PowerVia, and system-aware co-design, Intel is positioning itself to regain leadership in semiconductor manufacturing.
However, the path ahead is fraught with challenges:
- Sustaining yield improvements at scale
- Ensuring robust ecosystem support for novel flows
- Managing the cost and availability of high-NA EUV
For CTOs and system architects, the key takeaway is clear: the future of compute lies in tightly integrated, domain-optimized silicon-and-packaging solutions. Intel’s roadmap reflects this vision, and while execution risks remain, the technical foundation is undeniably strong.